Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M Platform: |
Size: 776642 |
Author:张涛 |
Hits:
Description: 在信息处理中,特别是实时视频图像处理中,通常都要对实现视频图像进行处理,而这首先必须设计大容量的存储器,同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点,但因SDRAM的控制结构复杂,常用的方法是设计SDRAM通用控制器,这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此,笔者在研究有关文献的基础上,根据具体情况提出一种独特的方法,实现了对SDRAM的控制,并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转,截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing. Platform: |
Size: 137216 |
Author:赵明玺 |
Hits:
Description: SDRAM控制器,以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz,我在实际工程中用到了120MHz,但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the 125MHz, I used in the actual works of 120MHz, but did not do test in 125MHz or more Platform: |
Size: 6203392 |
Author:何宗奎 |
Hits:
Description: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block Platform: |
Size: 2048 |
Author:Taher Aghazadeh |
Hits:
Description: 瑞芯科技EFX400SL开发板上使用ISE创建的SDRAM控制器的工程源码-Rockchip EFX400SL technology development board created by the use of ISE projects SDRAM controller source Platform: |
Size: 13446144 |
Author:曹晶 |
Hits:
Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is based Xilinx FPGA Playform. Platform: |
Size: 108544 |
Author:peace |
Hits:
Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform. Platform: |
Size: 488448 |
Author:peace |
Hits:
Description: 双端口SDRAM控制器,将SDRAM虚拟成两个端口,已经在ALTER DE2开发板的硬件上验证通过,采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language. Platform: |
Size: 11264 |
Author: |
Hits:
Description: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable Platform: |
Size: 37888 |
Author:james |
Hits:
Description: altera 公司sdr sdram 控制器源码,是VHDL的,大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download Platform: |
Size: 16384 |
Author:梦殇 |
Hits: